OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.k-LUT based FPGAs, combinational circuits, performance-driven mapping.

OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING

Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packagestwo-way partitioning, multi-way partitioning, recursive partitioning, flat partitioning, critical path, cutting cones, bottom-up clusters, top-down min-cut

INTELLIGENT LOW-POWER SMART HOME ARCHITECTURE

The Smart Home technology is a house that implements a variety of physical and digital well-integrated technologies, providing a number of functionalities like control of lighting, temperature, multimedia devices, flammable gas leakage, automatic plant irrigation or alarms security using a set of hardware components connected to a development board that can be accessed remotely through an Android application. First, is presented the context and a state-of-the-art for such of applications. Second, is made a description for the architecture hardware and software of a smart home application like custom. Finally, results are highlighted and some edifying conclusions

ELECTRICITY METER WITH THE FACILITY TO DETERMINE THE QUALITY OF THE ELECTRICITY SUPPLIED

Many areas of activity face the problem of electricity quality. At the same time, diagnosing the quality of the energy provided makes it possible to identify and remedy problems that have arisen in the system. Advanced signal processing techniques and the use of advanced systems allow for a complex analysis of the phenomenon. The paper presents an electricity meter equipped with an electricity quality analysis system. It was developed based on the Xilinx Artix-7 programmable logic matrix. A Digilent Arty A7 development board was used due to its design and experimentation facilities. The developed system determines the power consumed and the main elements that define the quality of electricity: harmonics and other deviations from the frequency of nominal power supply, flicker, voltage gaps, voltage variations, transient surge, temporary surge, etc. The possibility of using an embedded system equipped with the Microblaze soft microprocessor, the existence of a 12-bit analog-digital converter and the maximum sampling frequency of 1 MSPS and the possibility of assisted design allows to obtain a measurement system with superior characteristics. The results obtained and the experiments carried out confirm the expected performance for the electricity meter

INTELLIGENT LOW-POWER SMART HOME ARCHITECTURE

The Smart Home technology is a house that implements a variety of physical and digital well-integrated technologies, providing a number of functionalities like control of lighting, temperature, multimedia devices, flammable gas leakage, automatic plant irrigation or alarms security using a set of hardware components connected to a development board that can be accessed remotely through an Android application. First, is presented the context and a state-of-the-art for such of applications. Second, is made a description for the architecture hardware and software of a smart home application like custom. Finally, results are highlighted and some edifying conclusions

ENVIRONMENTAL TEMPERATURE AND HUMIDITY MONITORING SYSTEM USING RASPBERRY PI 4 AND THINGSPEACK

In recent years, IoT platforms have become increasingly used due to their untapped potential. This paper aims to create an IoT system to monitor temperature and humidity in an enclosure The Raspberry Pi 4 SBC (Single-Board Computer) development board and ThingSpeak cloud platform will be used to make this system. Data from the DHT11 humidity and temperature sensor will be collected by the Raspberry PI 4 SBC development board, which will transmit it via the WiFi connection to the IoT ThingSpeak platform cloud for further analysis. The IoT ThingSpeak platform provides data storage, processing and visualization services

Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits

The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay minimum solutions but having low used area

OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.k-LUT based FPGAs, combinational circuits, performance-driven mapping.

OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING

Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packagestwo-way partitioning, multi-way partitioning, recursive partitioning, flat partitioning, critical path, cutting cones, bottom-up clusters, top-down min-cut